1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same. In particular, the present invention relates to a lateral home-junction or hetero-junction bipolar transistor incorporating an SOI. (silicon on insulator) substrate, and a method for producing the same.
2. Description of the Related Art
FIG. 4 is a schematic cross-sectional view illustrating the structure of an npn-type vertical hetero-bipolar transistor (HBT) composed of SiGe/Si and produced by a conventional technique.
In accordance with this conventional vertical HBT, an n+ type Si collector contact layer 302, an nxe2x88x92 type Si collector layer 303, a p type SiGe true base region (layer) 304, a p+ type SiGe external base region (layer) 305, an n type Si emitter layer 306, and an n+ type Si emitter contact layer 307 are layered in this order on a silicon substrate 301. A collector electrode 308 is formed on an exposed surface of the n+ type Si collector contact layer 302 which is formed by local etching. A base electrode 309 is formed on an exposed surface of the p+ type SiGe external base region (layer) 305 which is also formed by local etching. Furthermore, an emitter electrode 310 is formed on the n+ type Si emitter contact layer 307.
During the operation of the HBT, electrons which have been implanted from the n type Si emitter layer 306 into the p type SiGe true base region (layer) 304 flow into n+ type Si collector layer 303 through diffusion, and drift as minority carriers, thereby providing a collector current. A portion of the electrons recombine inside, or in the vicinity of, the p type SiGe true base region (layer) 304 or the p+ type SiGe external base region (layer) 305, thereby providing a base current. Since the size of the collector current is in proportion with the size of the base current, it is possible with this HBT to amplify an external signal by modulating the base current in accordance with the external signal.
In accordance with an HT having the above-described structure, the base layers are formed of SiGe, so that the band gaps which exist between the base layers and the emitter layer in the valence band can be Increased relative to the case where the base layers are formed of Si. As a result, the flow of holes into the emitter layer is reduced, whereby the carrier concentration in the base layers is increased and the base resistance is reduced.
In order to improve the performance of semiconductor integrated circuits in general, bipolar transistors having excellent high-speed operation characteristics are desired. Accordingly, efforts are being made to improve the high-speed operation characteristics of bipolar transistor by reducing the thickness of base layer and reducing the base-emitter parasitic capacitance or the base-collector parasitic capacitance.
For example, in order to enable a high frequency operation of the HBT having the structure as shown in FIG. 4 and provide improved high frequency characteristics, it is essential to reduce the base running time of carriers and reduce the parasitic capacitance components and resistive components. In particular, in the case where the base resistance RB and the base-collector capacitance CBC are large, a large time constant (=RBxc2x7CBC) is created, resulting in deteriorated high frequency characteristics.
In order to reduce the base-emitter parasitic capacitance or the base-collector parasitic capacitance, it is necessary to minimize the area of the base-emitter junction. However, conventional methods employing photolithography techniques cannot create a junction portion which is smaller than is possible to create given the microprocessing subtlety level achieved by photolithography techniques.
Moreover, according to conventional methods, the base layer in a base-emitter junction portion and a base extension layer (i.e., a layer which extends from the base layer to a base electrode) are generally produced by using the same crystal growing step(s). Therefore, reducing the thickness of the base layer also results in the reduction of the thickness of the base extension layer. Since this increases the electric resistance of the base extension layer, the time constant which is determined as a function of the electric resistance component of the base extension layer and the base-emitter capacitance component is also increased, thereby hindering high-speed operations. In this regard, the thickness of the base layer can only be reduced to a certain extent under the conventional methods.
In the structure illustrated in FIG. 4, the p+ type SiGe external base region (layer) 305 having an enhanced p type carrier concentration is provided next to the p type SiGe true base region (layer) 304 in order to reduce the base resistance, and the base electrode 309 is formed on the p+ type SiGe external base region (layer) 305. However, in accordance with this structure, a base-collector capacitance is created between the p+ type SiGe external base region (layer) 305 and the n+ type Si collector contact layer 302, whose capacitance value increases as the carrier concentration in the p+ type SiGe external base region (layer) 305 is increased in order to decrease the base resistance. In other words, a trade-off relationship exists between the size of the base resistance and the size of the base-collector capacitance.
Furthermore, the high-speed operation characteristics of conventional devices are undermined due to the inter-device parasitic capacitance and the device-substrate parasitic capacitance.
According to one aspect of the present invention, there is provided a lateral bipolar transistor which includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed, so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening; and the first semiconductor region includes an emitter region and a collector region formed therein.
In one embodiment of the invention, the first semiconductor region is composed essentially of monocrystalline n type Si, and the second semiconductor region is composed essentially of p type SixGe1xe2x88x92x (where 0xe2x89xa6xxe2x89xa61).
In another embodiment of the invention, the lower portion of the second semiconductor region which at least fills the second opening has a multilayer structure at least including a first portion and a second portion, the first portion being tn contact with the face of the first semiconductor region defining the side wall of the second opening, and the second portion being in contact with the first portion.
In still another embodiment of the invention, the first portion is composed essentially of non-doped SiyGe1xe2x88x92y (where 0xe2x89xa6yxe2x89xa61), and the second portion is composed essentially of SixGe1xe2x88x92x (where 0xe2x89xa6xxe2x89xa61) of the second conductivity type.
In still another embodiment of the invention, the first portion is composed essentially of Si of the first conductivity type, and the second portion is composed essentially of SixGe1xe2x88x92x (where 0xe2x89xa6xxe2x89xa61) of the second conductivity type.
In still another embodiment of the invention, an upper portion of the second semiconductor region which fills the first opening of the second insulative region has a carrier concentration higher than a carrier concentration in the lower portion of the second semiconductor region which at least fills the second opening of the first semiconductor region.
In still another embodiment of the invention, an upper portion of the second semiconductor region which fills the first opening of the second insulative region has a carrier concentration higher than a carrier concentration in the lower portion of the second semiconductor region which at least fills the second opening of the first semiconductor region, and the upper portion of the second semiconductor region having the higher carrier concentration is also present on a surface of the second insulative region.
According to another aspect of the invention, there is provided a method for producing a lateral bipolar transistor, including the steps of: forming a first semiconductor region of a first conductive type on a first insulative region, the first insulative region being provided on a substrate; selectively providing a region to function as an emitter region and a region to function as a collector region in the first semiconductor region; forming a second insulative region so as to substantially cover the first semiconductor region; forming a first opening in the second insulative region so as to reach a surface of the first semiconductor region; forming a second opening in the first semiconductor region so as to reach the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; and selectively forming a second semiconductor region of a second conductivity type different from the first conductivity type so as to fill the first opening and the second opening, the second semiconductor functioning as a base region, wherein a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening.
In one embodiment of the invention, the first semiconductor region is composed essentially of monocrystalline n type Si, and the second semiconductor region is composed essentially of p type SixGe1xe2x88x92x (where 0xe2x89xa6xxe2x89xa61).
In another embodiment of the invention, the step of forming the second semiconductor region includes forming a multilayer structure as the second opening is filled, the multilayer structure at least including a first portion and a second portion such that the first portion is in contact with the face of the first semiconductor region defining the side wall of the second opening, and the second portion is in contact with the first portion.
In still another embodiment of the invention, the step of forming the multilayer structure includes forming the first portion from non-doped SiyGe1xe2x88x92y (where 0xe2x89xa6yxe2x89xa61), and forming the second portion from SixGe1xe2x88x92x (where 0xe2x89xa6xxe2x89xa61) of the second conductivity type.
In still another embodiment of the invention, the step of forming the multilayer structure includes forming the first portion from Si of the first conductivity type, and forming the second portion from SixGe1xe2x88x92x (where 0xe2x89xa6xxe2x89xa61) of the second conductivity type.
In still another embodiment of the invention, the second semiconductor region is formed in such a manner that an upper portion of the second semiconductor region which fills the first opening of the second insulative region has a carrier concentration higher than a carrier concentration in the lower portion of the second semiconductor region which at least fills the second opening of the first semiconductor region.
In still another embodiment of the invention, the step of forming the second semiconductor region includes: forming the lower portion of the second semiconductor region which at least fills the second opening by lateral growth from the face of the first semiconductor region defining the side wall of the second opening; and forming via a non-selective growth process an upper portion of the second semiconductor region which fills the first opening of the second insulative region so as to have a carrier concentration higher than a carrier concentration in the lower portion of the second semiconductor region, wherein the upper portion of the second semiconductor region having the higher carrier concentration is formed via the non-selective growth process so as to be also present on a surface of the second insulative region.
In still another embodiment of the invention, the step of forming the second opening includes removing via dry etching a portion of the first semiconductor region corresponding to the second opening, wherein the step of forming the second semiconductor region includes: performing a thermal treatment for attaining substantial recovery from damage which was inflicted during the dry etching on a portion corresponding to the side wall of the second opening; forming the second semiconductor region so as to fill the second opening after the thermal treatment; and further growing the second semiconductor region so as to fill the first opening of the second insulative region.
In still another embodiment of the invention, at least the region of the first semiconductor region to function as the emitter region is formed by impurity diffusion or ion implantation of a first impurity or ion into a first predetermined location within the first semiconductor region.
In still another embodiment of the invention, the method further includes the steps of: forming the region of the first semiconductor region to function as the emitter region by impurity diffusion or ion implantation of a first impurity or ion into a first predetermined location within the first semiconductor region; and forming the collector region by impurity diffusion or ion implantation of a second impurity or ion into a second predetermined location within the first semiconductor region, the first and second predetermined locations being different from each other, wherein the emitter region and the collector region have different carrier concentrations.
A lateral bipolar transistor which is produced according to the present invention includes an active region whose thickness is equal to the thickness of a device structural silicon layer which is formed on an oxidation film provided on an SOI substrate. Therefore, it is possible to reduce the thickness of the active region down to the minimum level that can be attained by polish processing techniques or oxygen injection techniques. Since the area of a base-emitter junction is determined depending on the thickness of the active region in accordance with the lateral bipolar transistor of the present invention, it is possible to reduce the area of the base-emitter junction as compared to that of a bipolar transistor which is produced by conventional lithography techniques.
Since there is no base extension layer is provided, an electrode ohmic contact can be directly formed with a true base layer. As a result, the base resistance is reduced thereby enabling a higher operation speed.
By employing an SOI substrate, a silicon oxide film provides electrical insulation can be obtained between devices or between the device and the substrate. As a result, inter-device parasitic capacitance and the device-substrate parasitic capacitance can be reduced, so that the high-speed operation characteristics that are inherent in each device can be adequately elicited.
Thus, the invention described herein makes possible the advantages of (1) providing a lateral bipolar transistor which has a small parasitic region and a very thin epitaxial base layer, the lateral bipolar transistor having improved high-speed operation characteristics; and a method for producing such a lateral bipolar transistor.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.